circuit MACArray :
  module MYMAC :
    input clock : Clock
    input reset : Reset
    output io : { macIO : { flip dataIn : SInt<8>, flip accIn : SInt<32>, flip switchw : UInt<1>, flip weightIn : SInt<8>, flip weightWe : UInt<1>, flip weightTag : UInt<8>, outDelay : SInt, dataDelay : SInt, switchDelay : UInt<1>, weightDelay : SInt, weightWeDelay : UInt<1>, weightTagDelay : UInt}}

    reg wbuf1 : SInt<8>, clock with :
      reset => (reset, asSInt(UInt<8>("h0"))) @[MAC.scala 45:29]
    reg wbuf2 : SInt<8>, clock with :
      reset => (reset, asSInt(UInt<8>("h0"))) @[MAC.scala 45:29]
    reg currentBufferReg : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 46:33]
    when io.macIO.switchw : @[MAC.scala 47:25]
      node _currentBufferReg_T = not(currentBufferReg) @[MAC.scala 48:25]
      currentBufferReg <= _currentBufferReg_T @[MAC.scala 48:22]
    node currenBuffer = xor(currentBufferReg, io.macIO.switchw) @[MAC.scala 51:39]
    node _T = eq(io.macIO.weightTag, UInt<2>("h2")) @[MAC.scala 53:47]
    node _T_1 = and(io.macIO.weightWe, _T) @[MAC.scala 53:26]
    when _T_1 : @[MAC.scala 53:67]
      node _T_2 = eq(currenBuffer, UInt<1>("h0")) @[MAC.scala 54:22]
      when _T_2 : @[MAC.scala 54:29]
        wbuf2 <= io.macIO.weightIn @[MAC.scala 55:13]
      else :
        wbuf1 <= io.macIO.weightIn @[MAC.scala 57:13]
    node _weight_T = eq(currenBuffer, UInt<1>("h0")) @[MAC.scala 61:32]
    node weight = mux(_weight_T, wbuf2, wbuf1) @[MAC.scala 61:19]
    node product = mul(weight, io.macIO.dataIn) @[MAC.scala 62:24]
    node _out_T = add(product, io.macIO.accIn) @[MAC.scala 63:21]
    node _out_T_1 = tail(_out_T, 1) @[MAC.scala 63:21]
    node out = asSInt(_out_T_1) @[MAC.scala 63:21]
    reg io_macIO_dataDelay_REG : SInt, clock with :
      reset => (reset, asSInt(UInt<1>("h0"))) @[MAC.scala 67:32]
    io_macIO_dataDelay_REG <= io.macIO.dataIn @[MAC.scala 67:32]
    io.macIO.dataDelay <= io_macIO_dataDelay_REG @[MAC.scala 67:22]
    reg io_macIO_switchDelay_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 68:34]
    io_macIO_switchDelay_REG <= io.macIO.switchw @[MAC.scala 68:34]
    io.macIO.switchDelay <= io_macIO_switchDelay_REG @[MAC.scala 68:24]
    reg io_macIO_outDelay_REG : SInt, clock with :
      reset => (reset, asSInt(UInt<1>("h0"))) @[MAC.scala 69:31]
    io_macIO_outDelay_REG <= out @[MAC.scala 69:31]
    io.macIO.outDelay <= io_macIO_outDelay_REG @[MAC.scala 69:21]
    reg io_macIO_weightDelay_REG : SInt, clock with :
      reset => (reset, asSInt(UInt<1>("h0"))) @[MAC.scala 70:34]
    io_macIO_weightDelay_REG <= io.macIO.weightIn @[MAC.scala 70:34]
    io.macIO.weightDelay <= io_macIO_weightDelay_REG @[MAC.scala 70:24]
    reg io_macIO_weightWeDelay_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 71:36]
    io_macIO_weightWeDelay_REG <= io.macIO.weightWe @[MAC.scala 71:36]
    io.macIO.weightWeDelay <= io_macIO_weightWeDelay_REG @[MAC.scala 71:26]
    node _io_macIO_weightTagDelay_T = add(io.macIO.weightTag, UInt<1>("h1")) @[MAC.scala 72:58]
    node _io_macIO_weightTagDelay_T_1 = tail(_io_macIO_weightTagDelay_T, 1) @[MAC.scala 72:58]
    reg io_macIO_weightTagDelay_REG : UInt, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 72:37]
    io_macIO_weightTagDelay_REG <= _io_macIO_weightTagDelay_T_1 @[MAC.scala 72:37]
    io.macIO.weightTagDelay <= io_macIO_weightTagDelay_REG @[MAC.scala 72:27]

  module MYMAC_1 :
    input clock : Clock
    input reset : Reset
    output io : { macIO : { flip dataIn : SInt<8>, flip accIn : SInt<32>, flip switchw : UInt<1>, flip weightIn : SInt<8>, flip weightWe : UInt<1>, flip weightTag : UInt<8>, outDelay : SInt, dataDelay : SInt, switchDelay : UInt<1>, weightDelay : SInt, weightWeDelay : UInt<1>, weightTagDelay : UInt}}

    reg wbuf1 : SInt<8>, clock with :
      reset => (reset, asSInt(UInt<8>("h0"))) @[MAC.scala 45:29]
    reg wbuf2 : SInt<8>, clock with :
      reset => (reset, asSInt(UInt<8>("h0"))) @[MAC.scala 45:29]
    reg currentBufferReg : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 46:33]
    when io.macIO.switchw : @[MAC.scala 47:25]
      node _currentBufferReg_T = not(currentBufferReg) @[MAC.scala 48:25]
      currentBufferReg <= _currentBufferReg_T @[MAC.scala 48:22]
    node currenBuffer = xor(currentBufferReg, io.macIO.switchw) @[MAC.scala 51:39]
    node _T = eq(io.macIO.weightTag, UInt<2>("h2")) @[MAC.scala 53:47]
    node _T_1 = and(io.macIO.weightWe, _T) @[MAC.scala 53:26]
    when _T_1 : @[MAC.scala 53:67]
      node _T_2 = eq(currenBuffer, UInt<1>("h0")) @[MAC.scala 54:22]
      when _T_2 : @[MAC.scala 54:29]
        wbuf2 <= io.macIO.weightIn @[MAC.scala 55:13]
      else :
        wbuf1 <= io.macIO.weightIn @[MAC.scala 57:13]
    node _weight_T = eq(currenBuffer, UInt<1>("h0")) @[MAC.scala 61:32]
    node weight = mux(_weight_T, wbuf2, wbuf1) @[MAC.scala 61:19]
    node product = mul(weight, io.macIO.dataIn) @[MAC.scala 62:24]
    node _out_T = add(product, io.macIO.accIn) @[MAC.scala 63:21]
    node _out_T_1 = tail(_out_T, 1) @[MAC.scala 63:21]
    node out = asSInt(_out_T_1) @[MAC.scala 63:21]
    reg io_macIO_dataDelay_REG : SInt, clock with :
      reset => (reset, asSInt(UInt<1>("h0"))) @[MAC.scala 67:32]
    io_macIO_dataDelay_REG <= io.macIO.dataIn @[MAC.scala 67:32]
    io.macIO.dataDelay <= io_macIO_dataDelay_REG @[MAC.scala 67:22]
    reg io_macIO_switchDelay_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 68:34]
    io_macIO_switchDelay_REG <= io.macIO.switchw @[MAC.scala 68:34]
    io.macIO.switchDelay <= io_macIO_switchDelay_REG @[MAC.scala 68:24]
    reg io_macIO_outDelay_REG : SInt, clock with :
      reset => (reset, asSInt(UInt<1>("h0"))) @[MAC.scala 69:31]
    io_macIO_outDelay_REG <= out @[MAC.scala 69:31]
    io.macIO.outDelay <= io_macIO_outDelay_REG @[MAC.scala 69:21]
    reg io_macIO_weightDelay_REG : SInt, clock with :
      reset => (reset, asSInt(UInt<1>("h0"))) @[MAC.scala 70:34]
    io_macIO_weightDelay_REG <= io.macIO.weightIn @[MAC.scala 70:34]
    io.macIO.weightDelay <= io_macIO_weightDelay_REG @[MAC.scala 70:24]
    reg io_macIO_weightWeDelay_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 71:36]
    io_macIO_weightWeDelay_REG <= io.macIO.weightWe @[MAC.scala 71:36]
    io.macIO.weightWeDelay <= io_macIO_weightWeDelay_REG @[MAC.scala 71:26]
    node _io_macIO_weightTagDelay_T = add(io.macIO.weightTag, UInt<1>("h1")) @[MAC.scala 72:58]
    node _io_macIO_weightTagDelay_T_1 = tail(_io_macIO_weightTagDelay_T, 1) @[MAC.scala 72:58]
    reg io_macIO_weightTagDelay_REG : UInt, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 72:37]
    io_macIO_weightTagDelay_REG <= _io_macIO_weightTagDelay_T_1 @[MAC.scala 72:37]
    io.macIO.weightTagDelay <= io_macIO_weightTagDelay_REG @[MAC.scala 72:27]

  module MYMAC_2 :
    input clock : Clock
    input reset : Reset
    output io : { macIO : { flip dataIn : SInt<8>, flip accIn : SInt<32>, flip switchw : UInt<1>, flip weightIn : SInt<8>, flip weightWe : UInt<1>, flip weightTag : UInt<8>, outDelay : SInt, dataDelay : SInt, switchDelay : UInt<1>, weightDelay : SInt, weightWeDelay : UInt<1>, weightTagDelay : UInt}}

    reg wbuf1 : SInt<8>, clock with :
      reset => (reset, asSInt(UInt<8>("h0"))) @[MAC.scala 45:29]
    reg wbuf2 : SInt<8>, clock with :
      reset => (reset, asSInt(UInt<8>("h0"))) @[MAC.scala 45:29]
    reg currentBufferReg : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 46:33]
    when io.macIO.switchw : @[MAC.scala 47:25]
      node _currentBufferReg_T = not(currentBufferReg) @[MAC.scala 48:25]
      currentBufferReg <= _currentBufferReg_T @[MAC.scala 48:22]
    node currenBuffer = xor(currentBufferReg, io.macIO.switchw) @[MAC.scala 51:39]
    node _T = eq(io.macIO.weightTag, UInt<2>("h2")) @[MAC.scala 53:47]
    node _T_1 = and(io.macIO.weightWe, _T) @[MAC.scala 53:26]
    when _T_1 : @[MAC.scala 53:67]
      node _T_2 = eq(currenBuffer, UInt<1>("h0")) @[MAC.scala 54:22]
      when _T_2 : @[MAC.scala 54:29]
        wbuf2 <= io.macIO.weightIn @[MAC.scala 55:13]
      else :
        wbuf1 <= io.macIO.weightIn @[MAC.scala 57:13]
    node _weight_T = eq(currenBuffer, UInt<1>("h0")) @[MAC.scala 61:32]
    node weight = mux(_weight_T, wbuf2, wbuf1) @[MAC.scala 61:19]
    node product = mul(weight, io.macIO.dataIn) @[MAC.scala 62:24]
    node _out_T = add(product, io.macIO.accIn) @[MAC.scala 63:21]
    node _out_T_1 = tail(_out_T, 1) @[MAC.scala 63:21]
    node out = asSInt(_out_T_1) @[MAC.scala 63:21]
    reg io_macIO_dataDelay_REG : SInt, clock with :
      reset => (reset, asSInt(UInt<1>("h0"))) @[MAC.scala 67:32]
    io_macIO_dataDelay_REG <= io.macIO.dataIn @[MAC.scala 67:32]
    io.macIO.dataDelay <= io_macIO_dataDelay_REG @[MAC.scala 67:22]
    reg io_macIO_switchDelay_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 68:34]
    io_macIO_switchDelay_REG <= io.macIO.switchw @[MAC.scala 68:34]
    io.macIO.switchDelay <= io_macIO_switchDelay_REG @[MAC.scala 68:24]
    reg io_macIO_outDelay_REG : SInt, clock with :
      reset => (reset, asSInt(UInt<1>("h0"))) @[MAC.scala 69:31]
    io_macIO_outDelay_REG <= out @[MAC.scala 69:31]
    io.macIO.outDelay <= io_macIO_outDelay_REG @[MAC.scala 69:21]
    reg io_macIO_weightDelay_REG : SInt, clock with :
      reset => (reset, asSInt(UInt<1>("h0"))) @[MAC.scala 70:34]
    io_macIO_weightDelay_REG <= io.macIO.weightIn @[MAC.scala 70:34]
    io.macIO.weightDelay <= io_macIO_weightDelay_REG @[MAC.scala 70:24]
    reg io_macIO_weightWeDelay_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 71:36]
    io_macIO_weightWeDelay_REG <= io.macIO.weightWe @[MAC.scala 71:36]
    io.macIO.weightWeDelay <= io_macIO_weightWeDelay_REG @[MAC.scala 71:26]
    node _io_macIO_weightTagDelay_T = add(io.macIO.weightTag, UInt<1>("h1")) @[MAC.scala 72:58]
    node _io_macIO_weightTagDelay_T_1 = tail(_io_macIO_weightTagDelay_T, 1) @[MAC.scala 72:58]
    reg io_macIO_weightTagDelay_REG : UInt, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 72:37]
    io_macIO_weightTagDelay_REG <= _io_macIO_weightTagDelay_T_1 @[MAC.scala 72:37]
    io.macIO.weightTagDelay <= io_macIO_weightTagDelay_REG @[MAC.scala 72:27]

  module MYMAC_3 :
    input clock : Clock
    input reset : Reset
    output io : { macIO : { flip dataIn : SInt<8>, flip accIn : SInt<32>, flip switchw : UInt<1>, flip weightIn : SInt<8>, flip weightWe : UInt<1>, flip weightTag : UInt<8>, outDelay : SInt, dataDelay : SInt, switchDelay : UInt<1>, weightDelay : SInt, weightWeDelay : UInt<1>, weightTagDelay : UInt}}

    reg wbuf1 : SInt<8>, clock with :
      reset => (reset, asSInt(UInt<8>("h0"))) @[MAC.scala 45:29]
    reg wbuf2 : SInt<8>, clock with :
      reset => (reset, asSInt(UInt<8>("h0"))) @[MAC.scala 45:29]
    reg currentBufferReg : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 46:33]
    when io.macIO.switchw : @[MAC.scala 47:25]
      node _currentBufferReg_T = not(currentBufferReg) @[MAC.scala 48:25]
      currentBufferReg <= _currentBufferReg_T @[MAC.scala 48:22]
    node currenBuffer = xor(currentBufferReg, io.macIO.switchw) @[MAC.scala 51:39]
    node _T = eq(io.macIO.weightTag, UInt<2>("h2")) @[MAC.scala 53:47]
    node _T_1 = and(io.macIO.weightWe, _T) @[MAC.scala 53:26]
    when _T_1 : @[MAC.scala 53:67]
      node _T_2 = eq(currenBuffer, UInt<1>("h0")) @[MAC.scala 54:22]
      when _T_2 : @[MAC.scala 54:29]
        wbuf2 <= io.macIO.weightIn @[MAC.scala 55:13]
      else :
        wbuf1 <= io.macIO.weightIn @[MAC.scala 57:13]
    node _weight_T = eq(currenBuffer, UInt<1>("h0")) @[MAC.scala 61:32]
    node weight = mux(_weight_T, wbuf2, wbuf1) @[MAC.scala 61:19]
    node product = mul(weight, io.macIO.dataIn) @[MAC.scala 62:24]
    node _out_T = add(product, io.macIO.accIn) @[MAC.scala 63:21]
    node _out_T_1 = tail(_out_T, 1) @[MAC.scala 63:21]
    node out = asSInt(_out_T_1) @[MAC.scala 63:21]
    reg io_macIO_dataDelay_REG : SInt, clock with :
      reset => (reset, asSInt(UInt<1>("h0"))) @[MAC.scala 67:32]
    io_macIO_dataDelay_REG <= io.macIO.dataIn @[MAC.scala 67:32]
    io.macIO.dataDelay <= io_macIO_dataDelay_REG @[MAC.scala 67:22]
    reg io_macIO_switchDelay_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 68:34]
    io_macIO_switchDelay_REG <= io.macIO.switchw @[MAC.scala 68:34]
    io.macIO.switchDelay <= io_macIO_switchDelay_REG @[MAC.scala 68:24]
    reg io_macIO_outDelay_REG : SInt, clock with :
      reset => (reset, asSInt(UInt<1>("h0"))) @[MAC.scala 69:31]
    io_macIO_outDelay_REG <= out @[MAC.scala 69:31]
    io.macIO.outDelay <= io_macIO_outDelay_REG @[MAC.scala 69:21]
    reg io_macIO_weightDelay_REG : SInt, clock with :
      reset => (reset, asSInt(UInt<1>("h0"))) @[MAC.scala 70:34]
    io_macIO_weightDelay_REG <= io.macIO.weightIn @[MAC.scala 70:34]
    io.macIO.weightDelay <= io_macIO_weightDelay_REG @[MAC.scala 70:24]
    reg io_macIO_weightWeDelay_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 71:36]
    io_macIO_weightWeDelay_REG <= io.macIO.weightWe @[MAC.scala 71:36]
    io.macIO.weightWeDelay <= io_macIO_weightWeDelay_REG @[MAC.scala 71:26]
    node _io_macIO_weightTagDelay_T = add(io.macIO.weightTag, UInt<1>("h1")) @[MAC.scala 72:58]
    node _io_macIO_weightTagDelay_T_1 = tail(_io_macIO_weightTagDelay_T, 1) @[MAC.scala 72:58]
    reg io_macIO_weightTagDelay_REG : UInt, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 72:37]
    io_macIO_weightTagDelay_REG <= _io_macIO_weightTagDelay_T_1 @[MAC.scala 72:37]
    io.macIO.weightTagDelay <= io_macIO_weightTagDelay_REG @[MAC.scala 72:27]

  module MYMAC_4 :
    input clock : Clock
    input reset : Reset
    output io : { macIO : { flip dataIn : SInt<8>, flip accIn : SInt<32>, flip switchw : UInt<1>, flip weightIn : SInt<8>, flip weightWe : UInt<1>, flip weightTag : UInt<8>, outDelay : SInt, dataDelay : SInt, switchDelay : UInt<1>, weightDelay : SInt, weightWeDelay : UInt<1>, weightTagDelay : UInt}}

    reg wbuf1 : SInt<8>, clock with :
      reset => (reset, asSInt(UInt<8>("h0"))) @[MAC.scala 45:29]
    reg wbuf2 : SInt<8>, clock with :
      reset => (reset, asSInt(UInt<8>("h0"))) @[MAC.scala 45:29]
    reg currentBufferReg : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 46:33]
    when io.macIO.switchw : @[MAC.scala 47:25]
      node _currentBufferReg_T = not(currentBufferReg) @[MAC.scala 48:25]
      currentBufferReg <= _currentBufferReg_T @[MAC.scala 48:22]
    node currenBuffer = xor(currentBufferReg, io.macIO.switchw) @[MAC.scala 51:39]
    node _T = eq(io.macIO.weightTag, UInt<2>("h2")) @[MAC.scala 53:47]
    node _T_1 = and(io.macIO.weightWe, _T) @[MAC.scala 53:26]
    when _T_1 : @[MAC.scala 53:67]
      node _T_2 = eq(currenBuffer, UInt<1>("h0")) @[MAC.scala 54:22]
      when _T_2 : @[MAC.scala 54:29]
        wbuf2 <= io.macIO.weightIn @[MAC.scala 55:13]
      else :
        wbuf1 <= io.macIO.weightIn @[MAC.scala 57:13]
    node _weight_T = eq(currenBuffer, UInt<1>("h0")) @[MAC.scala 61:32]
    node weight = mux(_weight_T, wbuf2, wbuf1) @[MAC.scala 61:19]
    node product = mul(weight, io.macIO.dataIn) @[MAC.scala 62:24]
    node _out_T = add(product, io.macIO.accIn) @[MAC.scala 63:21]
    node _out_T_1 = tail(_out_T, 1) @[MAC.scala 63:21]
    node out = asSInt(_out_T_1) @[MAC.scala 63:21]
    reg io_macIO_dataDelay_REG : SInt, clock with :
      reset => (reset, asSInt(UInt<1>("h0"))) @[MAC.scala 67:32]
    io_macIO_dataDelay_REG <= io.macIO.dataIn @[MAC.scala 67:32]
    io.macIO.dataDelay <= io_macIO_dataDelay_REG @[MAC.scala 67:22]
    reg io_macIO_switchDelay_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 68:34]
    io_macIO_switchDelay_REG <= io.macIO.switchw @[MAC.scala 68:34]
    io.macIO.switchDelay <= io_macIO_switchDelay_REG @[MAC.scala 68:24]
    reg io_macIO_outDelay_REG : SInt, clock with :
      reset => (reset, asSInt(UInt<1>("h0"))) @[MAC.scala 69:31]
    io_macIO_outDelay_REG <= out @[MAC.scala 69:31]
    io.macIO.outDelay <= io_macIO_outDelay_REG @[MAC.scala 69:21]
    reg io_macIO_weightDelay_REG : SInt, clock with :
      reset => (reset, asSInt(UInt<1>("h0"))) @[MAC.scala 70:34]
    io_macIO_weightDelay_REG <= io.macIO.weightIn @[MAC.scala 70:34]
    io.macIO.weightDelay <= io_macIO_weightDelay_REG @[MAC.scala 70:24]
    reg io_macIO_weightWeDelay_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 71:36]
    io_macIO_weightWeDelay_REG <= io.macIO.weightWe @[MAC.scala 71:36]
    io.macIO.weightWeDelay <= io_macIO_weightWeDelay_REG @[MAC.scala 71:26]
    node _io_macIO_weightTagDelay_T = add(io.macIO.weightTag, UInt<1>("h1")) @[MAC.scala 72:58]
    node _io_macIO_weightTagDelay_T_1 = tail(_io_macIO_weightTagDelay_T, 1) @[MAC.scala 72:58]
    reg io_macIO_weightTagDelay_REG : UInt, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 72:37]
    io_macIO_weightTagDelay_REG <= _io_macIO_weightTagDelay_T_1 @[MAC.scala 72:37]
    io.macIO.weightTagDelay <= io_macIO_weightTagDelay_REG @[MAC.scala 72:27]

  module MYMAC_5 :
    input clock : Clock
    input reset : Reset
    output io : { macIO : { flip dataIn : SInt<8>, flip accIn : SInt<32>, flip switchw : UInt<1>, flip weightIn : SInt<8>, flip weightWe : UInt<1>, flip weightTag : UInt<8>, outDelay : SInt, dataDelay : SInt, switchDelay : UInt<1>, weightDelay : SInt, weightWeDelay : UInt<1>, weightTagDelay : UInt}}

    reg wbuf1 : SInt<8>, clock with :
      reset => (reset, asSInt(UInt<8>("h0"))) @[MAC.scala 45:29]
    reg wbuf2 : SInt<8>, clock with :
      reset => (reset, asSInt(UInt<8>("h0"))) @[MAC.scala 45:29]
    reg currentBufferReg : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 46:33]
    when io.macIO.switchw : @[MAC.scala 47:25]
      node _currentBufferReg_T = not(currentBufferReg) @[MAC.scala 48:25]
      currentBufferReg <= _currentBufferReg_T @[MAC.scala 48:22]
    node currenBuffer = xor(currentBufferReg, io.macIO.switchw) @[MAC.scala 51:39]
    node _T = eq(io.macIO.weightTag, UInt<2>("h2")) @[MAC.scala 53:47]
    node _T_1 = and(io.macIO.weightWe, _T) @[MAC.scala 53:26]
    when _T_1 : @[MAC.scala 53:67]
      node _T_2 = eq(currenBuffer, UInt<1>("h0")) @[MAC.scala 54:22]
      when _T_2 : @[MAC.scala 54:29]
        wbuf2 <= io.macIO.weightIn @[MAC.scala 55:13]
      else :
        wbuf1 <= io.macIO.weightIn @[MAC.scala 57:13]
    node _weight_T = eq(currenBuffer, UInt<1>("h0")) @[MAC.scala 61:32]
    node weight = mux(_weight_T, wbuf2, wbuf1) @[MAC.scala 61:19]
    node product = mul(weight, io.macIO.dataIn) @[MAC.scala 62:24]
    node _out_T = add(product, io.macIO.accIn) @[MAC.scala 63:21]
    node _out_T_1 = tail(_out_T, 1) @[MAC.scala 63:21]
    node out = asSInt(_out_T_1) @[MAC.scala 63:21]
    reg io_macIO_dataDelay_REG : SInt, clock with :
      reset => (reset, asSInt(UInt<1>("h0"))) @[MAC.scala 67:32]
    io_macIO_dataDelay_REG <= io.macIO.dataIn @[MAC.scala 67:32]
    io.macIO.dataDelay <= io_macIO_dataDelay_REG @[MAC.scala 67:22]
    reg io_macIO_switchDelay_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 68:34]
    io_macIO_switchDelay_REG <= io.macIO.switchw @[MAC.scala 68:34]
    io.macIO.switchDelay <= io_macIO_switchDelay_REG @[MAC.scala 68:24]
    reg io_macIO_outDelay_REG : SInt, clock with :
      reset => (reset, asSInt(UInt<1>("h0"))) @[MAC.scala 69:31]
    io_macIO_outDelay_REG <= out @[MAC.scala 69:31]
    io.macIO.outDelay <= io_macIO_outDelay_REG @[MAC.scala 69:21]
    reg io_macIO_weightDelay_REG : SInt, clock with :
      reset => (reset, asSInt(UInt<1>("h0"))) @[MAC.scala 70:34]
    io_macIO_weightDelay_REG <= io.macIO.weightIn @[MAC.scala 70:34]
    io.macIO.weightDelay <= io_macIO_weightDelay_REG @[MAC.scala 70:24]
    reg io_macIO_weightWeDelay_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 71:36]
    io_macIO_weightWeDelay_REG <= io.macIO.weightWe @[MAC.scala 71:36]
    io.macIO.weightWeDelay <= io_macIO_weightWeDelay_REG @[MAC.scala 71:26]
    node _io_macIO_weightTagDelay_T = add(io.macIO.weightTag, UInt<1>("h1")) @[MAC.scala 72:58]
    node _io_macIO_weightTagDelay_T_1 = tail(_io_macIO_weightTagDelay_T, 1) @[MAC.scala 72:58]
    reg io_macIO_weightTagDelay_REG : UInt, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 72:37]
    io_macIO_weightTagDelay_REG <= _io_macIO_weightTagDelay_T_1 @[MAC.scala 72:37]
    io.macIO.weightTagDelay <= io_macIO_weightTagDelay_REG @[MAC.scala 72:27]

  module MYMAC_6 :
    input clock : Clock
    input reset : Reset
    output io : { macIO : { flip dataIn : SInt<8>, flip accIn : SInt<32>, flip switchw : UInt<1>, flip weightIn : SInt<8>, flip weightWe : UInt<1>, flip weightTag : UInt<8>, outDelay : SInt, dataDelay : SInt, switchDelay : UInt<1>, weightDelay : SInt, weightWeDelay : UInt<1>, weightTagDelay : UInt}}

    reg wbuf1 : SInt<8>, clock with :
      reset => (reset, asSInt(UInt<8>("h0"))) @[MAC.scala 45:29]
    reg wbuf2 : SInt<8>, clock with :
      reset => (reset, asSInt(UInt<8>("h0"))) @[MAC.scala 45:29]
    reg currentBufferReg : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 46:33]
    when io.macIO.switchw : @[MAC.scala 47:25]
      node _currentBufferReg_T = not(currentBufferReg) @[MAC.scala 48:25]
      currentBufferReg <= _currentBufferReg_T @[MAC.scala 48:22]
    node currenBuffer = xor(currentBufferReg, io.macIO.switchw) @[MAC.scala 51:39]
    node _T = eq(io.macIO.weightTag, UInt<2>("h2")) @[MAC.scala 53:47]
    node _T_1 = and(io.macIO.weightWe, _T) @[MAC.scala 53:26]
    when _T_1 : @[MAC.scala 53:67]
      node _T_2 = eq(currenBuffer, UInt<1>("h0")) @[MAC.scala 54:22]
      when _T_2 : @[MAC.scala 54:29]
        wbuf2 <= io.macIO.weightIn @[MAC.scala 55:13]
      else :
        wbuf1 <= io.macIO.weightIn @[MAC.scala 57:13]
    node _weight_T = eq(currenBuffer, UInt<1>("h0")) @[MAC.scala 61:32]
    node weight = mux(_weight_T, wbuf2, wbuf1) @[MAC.scala 61:19]
    node product = mul(weight, io.macIO.dataIn) @[MAC.scala 62:24]
    node _out_T = add(product, io.macIO.accIn) @[MAC.scala 63:21]
    node _out_T_1 = tail(_out_T, 1) @[MAC.scala 63:21]
    node out = asSInt(_out_T_1) @[MAC.scala 63:21]
    reg io_macIO_dataDelay_REG : SInt, clock with :
      reset => (reset, asSInt(UInt<1>("h0"))) @[MAC.scala 67:32]
    io_macIO_dataDelay_REG <= io.macIO.dataIn @[MAC.scala 67:32]
    io.macIO.dataDelay <= io_macIO_dataDelay_REG @[MAC.scala 67:22]
    reg io_macIO_switchDelay_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 68:34]
    io_macIO_switchDelay_REG <= io.macIO.switchw @[MAC.scala 68:34]
    io.macIO.switchDelay <= io_macIO_switchDelay_REG @[MAC.scala 68:24]
    reg io_macIO_outDelay_REG : SInt, clock with :
      reset => (reset, asSInt(UInt<1>("h0"))) @[MAC.scala 69:31]
    io_macIO_outDelay_REG <= out @[MAC.scala 69:31]
    io.macIO.outDelay <= io_macIO_outDelay_REG @[MAC.scala 69:21]
    reg io_macIO_weightDelay_REG : SInt, clock with :
      reset => (reset, asSInt(UInt<1>("h0"))) @[MAC.scala 70:34]
    io_macIO_weightDelay_REG <= io.macIO.weightIn @[MAC.scala 70:34]
    io.macIO.weightDelay <= io_macIO_weightDelay_REG @[MAC.scala 70:24]
    reg io_macIO_weightWeDelay_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 71:36]
    io_macIO_weightWeDelay_REG <= io.macIO.weightWe @[MAC.scala 71:36]
    io.macIO.weightWeDelay <= io_macIO_weightWeDelay_REG @[MAC.scala 71:26]
    node _io_macIO_weightTagDelay_T = add(io.macIO.weightTag, UInt<1>("h1")) @[MAC.scala 72:58]
    node _io_macIO_weightTagDelay_T_1 = tail(_io_macIO_weightTagDelay_T, 1) @[MAC.scala 72:58]
    reg io_macIO_weightTagDelay_REG : UInt, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 72:37]
    io_macIO_weightTagDelay_REG <= _io_macIO_weightTagDelay_T_1 @[MAC.scala 72:37]
    io.macIO.weightTagDelay <= io_macIO_weightTagDelay_REG @[MAC.scala 72:27]

  module MYMAC_7 :
    input clock : Clock
    input reset : Reset
    output io : { macIO : { flip dataIn : SInt<8>, flip accIn : SInt<32>, flip switchw : UInt<1>, flip weightIn : SInt<8>, flip weightWe : UInt<1>, flip weightTag : UInt<8>, outDelay : SInt, dataDelay : SInt, switchDelay : UInt<1>, weightDelay : SInt, weightWeDelay : UInt<1>, weightTagDelay : UInt}}

    reg wbuf1 : SInt<8>, clock with :
      reset => (reset, asSInt(UInt<8>("h0"))) @[MAC.scala 45:29]
    reg wbuf2 : SInt<8>, clock with :
      reset => (reset, asSInt(UInt<8>("h0"))) @[MAC.scala 45:29]
    reg currentBufferReg : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 46:33]
    when io.macIO.switchw : @[MAC.scala 47:25]
      node _currentBufferReg_T = not(currentBufferReg) @[MAC.scala 48:25]
      currentBufferReg <= _currentBufferReg_T @[MAC.scala 48:22]
    node currenBuffer = xor(currentBufferReg, io.macIO.switchw) @[MAC.scala 51:39]
    node _T = eq(io.macIO.weightTag, UInt<2>("h2")) @[MAC.scala 53:47]
    node _T_1 = and(io.macIO.weightWe, _T) @[MAC.scala 53:26]
    when _T_1 : @[MAC.scala 53:67]
      node _T_2 = eq(currenBuffer, UInt<1>("h0")) @[MAC.scala 54:22]
      when _T_2 : @[MAC.scala 54:29]
        wbuf2 <= io.macIO.weightIn @[MAC.scala 55:13]
      else :
        wbuf1 <= io.macIO.weightIn @[MAC.scala 57:13]
    node _weight_T = eq(currenBuffer, UInt<1>("h0")) @[MAC.scala 61:32]
    node weight = mux(_weight_T, wbuf2, wbuf1) @[MAC.scala 61:19]
    node product = mul(weight, io.macIO.dataIn) @[MAC.scala 62:24]
    node _out_T = add(product, io.macIO.accIn) @[MAC.scala 63:21]
    node _out_T_1 = tail(_out_T, 1) @[MAC.scala 63:21]
    node out = asSInt(_out_T_1) @[MAC.scala 63:21]
    reg io_macIO_dataDelay_REG : SInt, clock with :
      reset => (reset, asSInt(UInt<1>("h0"))) @[MAC.scala 67:32]
    io_macIO_dataDelay_REG <= io.macIO.dataIn @[MAC.scala 67:32]
    io.macIO.dataDelay <= io_macIO_dataDelay_REG @[MAC.scala 67:22]
    reg io_macIO_switchDelay_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 68:34]
    io_macIO_switchDelay_REG <= io.macIO.switchw @[MAC.scala 68:34]
    io.macIO.switchDelay <= io_macIO_switchDelay_REG @[MAC.scala 68:24]
    reg io_macIO_outDelay_REG : SInt, clock with :
      reset => (reset, asSInt(UInt<1>("h0"))) @[MAC.scala 69:31]
    io_macIO_outDelay_REG <= out @[MAC.scala 69:31]
    io.macIO.outDelay <= io_macIO_outDelay_REG @[MAC.scala 69:21]
    reg io_macIO_weightDelay_REG : SInt, clock with :
      reset => (reset, asSInt(UInt<1>("h0"))) @[MAC.scala 70:34]
    io_macIO_weightDelay_REG <= io.macIO.weightIn @[MAC.scala 70:34]
    io.macIO.weightDelay <= io_macIO_weightDelay_REG @[MAC.scala 70:24]
    reg io_macIO_weightWeDelay_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 71:36]
    io_macIO_weightWeDelay_REG <= io.macIO.weightWe @[MAC.scala 71:36]
    io.macIO.weightWeDelay <= io_macIO_weightWeDelay_REG @[MAC.scala 71:26]
    node _io_macIO_weightTagDelay_T = add(io.macIO.weightTag, UInt<1>("h1")) @[MAC.scala 72:58]
    node _io_macIO_weightTagDelay_T_1 = tail(_io_macIO_weightTagDelay_T, 1) @[MAC.scala 72:58]
    reg io_macIO_weightTagDelay_REG : UInt, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 72:37]
    io_macIO_weightTagDelay_REG <= _io_macIO_weightTagDelay_T_1 @[MAC.scala 72:37]
    io.macIO.weightTagDelay <= io_macIO_weightTagDelay_REG @[MAC.scala 72:27]

  module MYMAC_8 :
    input clock : Clock
    input reset : Reset
    output io : { macIO : { flip dataIn : SInt<8>, flip accIn : SInt<32>, flip switchw : UInt<1>, flip weightIn : SInt<8>, flip weightWe : UInt<1>, flip weightTag : UInt<8>, outDelay : SInt, dataDelay : SInt, switchDelay : UInt<1>, weightDelay : SInt, weightWeDelay : UInt<1>, weightTagDelay : UInt}}

    reg wbuf1 : SInt<8>, clock with :
      reset => (reset, asSInt(UInt<8>("h0"))) @[MAC.scala 45:29]
    reg wbuf2 : SInt<8>, clock with :
      reset => (reset, asSInt(UInt<8>("h0"))) @[MAC.scala 45:29]
    reg currentBufferReg : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 46:33]
    when io.macIO.switchw : @[MAC.scala 47:25]
      node _currentBufferReg_T = not(currentBufferReg) @[MAC.scala 48:25]
      currentBufferReg <= _currentBufferReg_T @[MAC.scala 48:22]
    node currenBuffer = xor(currentBufferReg, io.macIO.switchw) @[MAC.scala 51:39]
    node _T = eq(io.macIO.weightTag, UInt<2>("h2")) @[MAC.scala 53:47]
    node _T_1 = and(io.macIO.weightWe, _T) @[MAC.scala 53:26]
    when _T_1 : @[MAC.scala 53:67]
      node _T_2 = eq(currenBuffer, UInt<1>("h0")) @[MAC.scala 54:22]
      when _T_2 : @[MAC.scala 54:29]
        wbuf2 <= io.macIO.weightIn @[MAC.scala 55:13]
      else :
        wbuf1 <= io.macIO.weightIn @[MAC.scala 57:13]
    node _weight_T = eq(currenBuffer, UInt<1>("h0")) @[MAC.scala 61:32]
    node weight = mux(_weight_T, wbuf2, wbuf1) @[MAC.scala 61:19]
    node product = mul(weight, io.macIO.dataIn) @[MAC.scala 62:24]
    node _out_T = add(product, io.macIO.accIn) @[MAC.scala 63:21]
    node _out_T_1 = tail(_out_T, 1) @[MAC.scala 63:21]
    node out = asSInt(_out_T_1) @[MAC.scala 63:21]
    reg io_macIO_dataDelay_REG : SInt, clock with :
      reset => (reset, asSInt(UInt<1>("h0"))) @[MAC.scala 67:32]
    io_macIO_dataDelay_REG <= io.macIO.dataIn @[MAC.scala 67:32]
    io.macIO.dataDelay <= io_macIO_dataDelay_REG @[MAC.scala 67:22]
    reg io_macIO_switchDelay_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 68:34]
    io_macIO_switchDelay_REG <= io.macIO.switchw @[MAC.scala 68:34]
    io.macIO.switchDelay <= io_macIO_switchDelay_REG @[MAC.scala 68:24]
    reg io_macIO_outDelay_REG : SInt, clock with :
      reset => (reset, asSInt(UInt<1>("h0"))) @[MAC.scala 69:31]
    io_macIO_outDelay_REG <= out @[MAC.scala 69:31]
    io.macIO.outDelay <= io_macIO_outDelay_REG @[MAC.scala 69:21]
    reg io_macIO_weightDelay_REG : SInt, clock with :
      reset => (reset, asSInt(UInt<1>("h0"))) @[MAC.scala 70:34]
    io_macIO_weightDelay_REG <= io.macIO.weightIn @[MAC.scala 70:34]
    io.macIO.weightDelay <= io_macIO_weightDelay_REG @[MAC.scala 70:24]
    reg io_macIO_weightWeDelay_REG : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 71:36]
    io_macIO_weightWeDelay_REG <= io.macIO.weightWe @[MAC.scala 71:36]
    io.macIO.weightWeDelay <= io_macIO_weightWeDelay_REG @[MAC.scala 71:26]
    node _io_macIO_weightTagDelay_T = add(io.macIO.weightTag, UInt<1>("h1")) @[MAC.scala 72:58]
    node _io_macIO_weightTagDelay_T_1 = tail(_io_macIO_weightTagDelay_T, 1) @[MAC.scala 72:58]
    reg io_macIO_weightTagDelay_REG : UInt, clock with :
      reset => (reset, UInt<1>("h0")) @[MAC.scala 72:37]
    io_macIO_weightTagDelay_REG <= _io_macIO_weightTagDelay_T_1 @[MAC.scala 72:37]
    io.macIO.weightTagDelay <= io_macIO_weightTagDelay_REG @[MAC.scala 72:27]

  module MACArray :
    input clock : Clock
    input reset : UInt<1>
    output io : { flip dataIn : SInt<8>[3], flip switchw : UInt<1>[3], flip weightIn : SInt<8>[3], flip weightWe : UInt<1>, dataOut : SInt[3]}

    inst MYMAC of MYMAC @[MACArray.scala 21:15]
    MYMAC.clock <= clock
    MYMAC.reset <= reset
    inst MYMAC_1 of MYMAC_1 @[MACArray.scala 21:15]
    MYMAC_1.clock <= clock
    MYMAC_1.reset <= reset
    inst MYMAC_2 of MYMAC_2 @[MACArray.scala 21:15]
    MYMAC_2.clock <= clock
    MYMAC_2.reset <= reset
    inst MYMAC_3 of MYMAC_3 @[MACArray.scala 21:15]
    MYMAC_3.clock <= clock
    MYMAC_3.reset <= reset
    inst MYMAC_4 of MYMAC_4 @[MACArray.scala 21:15]
    MYMAC_4.clock <= clock
    MYMAC_4.reset <= reset
    inst MYMAC_5 of MYMAC_5 @[MACArray.scala 21:15]
    MYMAC_5.clock <= clock
    MYMAC_5.reset <= reset
    inst MYMAC_6 of MYMAC_6 @[MACArray.scala 21:15]
    MYMAC_6.clock <= clock
    MYMAC_6.reset <= reset
    inst MYMAC_7 of MYMAC_7 @[MACArray.scala 21:15]
    MYMAC_7.clock <= clock
    MYMAC_7.reset <= reset
    inst MYMAC_8 of MYMAC_8 @[MACArray.scala 21:15]
    MYMAC_8.clock <= clock
    MYMAC_8.reset <= reset
    wire weightWes : UInt<1>[3] @[MACArray.scala 24:25]
    reg programming : UInt<1>, clock with :
      reset => (reset, UInt<1>("h0")) @[MACArray.scala 25:30]
    reg progstep : UInt<2>, clock with :
      reset => (reset, UInt<2>("h0")) @[MACArray.scala 26:27]
    wire weightTags : UInt<2>[3] @[MACArray.scala 27:26]
    node _T = eq(programming, UInt<1>("h0")) @[MACArray.scala 30:36]
    node _T_1 = and(io.weightWe, _T) @[MACArray.scala 30:22]
    when _T_1 : @[MACArray.scala 30:48]
      programming <= UInt<1>("h1") @[MACArray.scala 31:21]
    else :
      node _T_2 = eq(programming, UInt<1>("h1")) @[MACArray.scala 32:28]
      node _T_3 = eq(progstep, UInt<2>("h2")) @[MACArray.scala 32:52]
      node _T_4 = and(_T_2, _T_3) @[MACArray.scala 32:40]
      when _T_4 : @[MACArray.scala 32:73]
        programming <= UInt<1>("h0") @[MACArray.scala 33:21]
    node _T_5 = eq(programming, UInt<1>("h1")) @[MACArray.scala 36:21]
    when _T_5 : @[MACArray.scala 36:33]
      node _progstep_T = add(progstep, UInt<1>("h1")) @[MACArray.scala 37:30]
      node _progstep_T_1 = tail(_progstep_T, 1) @[MACArray.scala 37:30]
      progstep <= _progstep_T_1 @[MACArray.scala 37:18]
    else :
      progstep <= UInt<1>("h0") @[MACArray.scala 39:18]
    weightWes[0] <= programming @[MACArray.scala 44:22]
    weightTags[0] <= progstep @[MACArray.scala 45:23]
    weightWes[1] <= programming @[MACArray.scala 44:22]
    weightTags[1] <= progstep @[MACArray.scala 45:23]
    weightWes[2] <= programming @[MACArray.scala 44:22]
    weightTags[2] <= progstep @[MACArray.scala 45:23]
    MYMAC_3.io.macIO.weightIn <= MYMAC.io.macIO.weightDelay @[MACArray.scala 58:56]
    MYMAC_3.io.macIO.weightWe <= MYMAC.io.macIO.weightWeDelay @[MACArray.scala 59:56]
    MYMAC_3.io.macIO.accIn <= MYMAC.io.macIO.outDelay @[MACArray.scala 60:53]
    MYMAC_3.io.macIO.weightTag <= MYMAC.io.macIO.weightTagDelay @[MACArray.scala 61:57]
    MYMAC_4.io.macIO.weightIn <= MYMAC_1.io.macIO.weightDelay @[MACArray.scala 58:56]
    MYMAC_4.io.macIO.weightWe <= MYMAC_1.io.macIO.weightWeDelay @[MACArray.scala 59:56]
    MYMAC_4.io.macIO.accIn <= MYMAC_1.io.macIO.outDelay @[MACArray.scala 60:53]
    MYMAC_4.io.macIO.weightTag <= MYMAC_1.io.macIO.weightTagDelay @[MACArray.scala 61:57]
    MYMAC_5.io.macIO.weightIn <= MYMAC_2.io.macIO.weightDelay @[MACArray.scala 58:56]
    MYMAC_5.io.macIO.weightWe <= MYMAC_2.io.macIO.weightWeDelay @[MACArray.scala 59:56]
    MYMAC_5.io.macIO.accIn <= MYMAC_2.io.macIO.outDelay @[MACArray.scala 60:53]
    MYMAC_5.io.macIO.weightTag <= MYMAC_2.io.macIO.weightTagDelay @[MACArray.scala 61:57]
    MYMAC_6.io.macIO.weightIn <= MYMAC_3.io.macIO.weightDelay @[MACArray.scala 58:56]
    MYMAC_6.io.macIO.weightWe <= MYMAC_3.io.macIO.weightWeDelay @[MACArray.scala 59:56]
    MYMAC_6.io.macIO.accIn <= MYMAC_3.io.macIO.outDelay @[MACArray.scala 60:53]
    MYMAC_6.io.macIO.weightTag <= MYMAC_3.io.macIO.weightTagDelay @[MACArray.scala 61:57]
    MYMAC_7.io.macIO.weightIn <= MYMAC_4.io.macIO.weightDelay @[MACArray.scala 58:56]
    MYMAC_7.io.macIO.weightWe <= MYMAC_4.io.macIO.weightWeDelay @[MACArray.scala 59:56]
    MYMAC_7.io.macIO.accIn <= MYMAC_4.io.macIO.outDelay @[MACArray.scala 60:53]
    MYMAC_7.io.macIO.weightTag <= MYMAC_4.io.macIO.weightTagDelay @[MACArray.scala 61:57]
    MYMAC_8.io.macIO.weightIn <= MYMAC_5.io.macIO.weightDelay @[MACArray.scala 58:56]
    MYMAC_8.io.macIO.weightWe <= MYMAC_5.io.macIO.weightWeDelay @[MACArray.scala 59:56]
    MYMAC_8.io.macIO.accIn <= MYMAC_5.io.macIO.outDelay @[MACArray.scala 60:53]
    MYMAC_8.io.macIO.weightTag <= MYMAC_5.io.macIO.weightTagDelay @[MACArray.scala 61:57]
    MYMAC_1.io.macIO.dataIn <= MYMAC.io.macIO.dataDelay @[MACArray.scala 68:52]
    MYMAC_1.io.macIO.switchw <= MYMAC.io.macIO.switchDelay @[MACArray.scala 69:53]
    MYMAC_2.io.macIO.dataIn <= MYMAC_1.io.macIO.dataDelay @[MACArray.scala 68:52]
    MYMAC_2.io.macIO.switchw <= MYMAC_1.io.macIO.switchDelay @[MACArray.scala 69:53]
    MYMAC_4.io.macIO.dataIn <= MYMAC_3.io.macIO.dataDelay @[MACArray.scala 68:52]
    MYMAC_4.io.macIO.switchw <= MYMAC_3.io.macIO.switchDelay @[MACArray.scala 69:53]
    MYMAC_5.io.macIO.dataIn <= MYMAC_4.io.macIO.dataDelay @[MACArray.scala 68:52]
    MYMAC_5.io.macIO.switchw <= MYMAC_4.io.macIO.switchDelay @[MACArray.scala 69:53]
    MYMAC_7.io.macIO.dataIn <= MYMAC_6.io.macIO.dataDelay @[MACArray.scala 68:52]
    MYMAC_7.io.macIO.switchw <= MYMAC_6.io.macIO.switchDelay @[MACArray.scala 69:53]
    MYMAC_8.io.macIO.dataIn <= MYMAC_7.io.macIO.dataDelay @[MACArray.scala 68:52]
    MYMAC_8.io.macIO.switchw <= MYMAC_7.io.macIO.switchDelay @[MACArray.scala 69:53]
    io.dataOut[0] <= MYMAC_6.io.macIO.outDelay @[MACArray.scala 75:23]
    io.dataOut[1] <= MYMAC_7.io.macIO.outDelay @[MACArray.scala 75:23]
    io.dataOut[2] <= MYMAC_8.io.macIO.outDelay @[MACArray.scala 75:23]
    MYMAC.io.macIO.dataIn <= io.dataIn[0] @[MACArray.scala 80:44]
    MYMAC.io.macIO.switchw <= io.switchw[0] @[MACArray.scala 81:45]
    MYMAC_3.io.macIO.dataIn <= io.dataIn[1] @[MACArray.scala 80:44]
    MYMAC_3.io.macIO.switchw <= io.switchw[1] @[MACArray.scala 81:45]
    MYMAC_6.io.macIO.dataIn <= io.dataIn[2] @[MACArray.scala 80:44]
    MYMAC_6.io.macIO.switchw <= io.switchw[2] @[MACArray.scala 81:45]
    MYMAC.io.macIO.accIn <= asSInt(UInt<32>("h0")) @[MACArray.scala 91:32]
    MYMAC.io.macIO.weightWe <= weightWes[0] @[MACArray.scala 92:35]
    MYMAC.io.macIO.weightIn <= io.weightIn[0] @[MACArray.scala 93:35]
    MYMAC.io.macIO.weightTag <= weightTags[0] @[MACArray.scala 94:36]
    MYMAC_1.io.macIO.accIn <= asSInt(UInt<32>("h0")) @[MACArray.scala 91:32]
    MYMAC_1.io.macIO.weightWe <= weightWes[1] @[MACArray.scala 92:35]
    MYMAC_1.io.macIO.weightIn <= io.weightIn[1] @[MACArray.scala 93:35]
    MYMAC_1.io.macIO.weightTag <= weightTags[1] @[MACArray.scala 94:36]
    MYMAC_2.io.macIO.accIn <= asSInt(UInt<32>("h0")) @[MACArray.scala 91:32]
    MYMAC_2.io.macIO.weightWe <= weightWes[2] @[MACArray.scala 92:35]
    MYMAC_2.io.macIO.weightIn <= io.weightIn[2] @[MACArray.scala 93:35]
    MYMAC_2.io.macIO.weightTag <= weightTags[2] @[MACArray.scala 94:36]

